Process and device technology have been developed to improve the performance of large scale integrated circuits. Increasing the density of MOS devices and LSI circuits result in improved higher speeds of operation.
Nonplanar-type devices have been proposed for such high performance LSI circuits, including a nonplanar diffusion self-aligned (DSA) MOS transistor and a VMOS transistor. These two nonplanar devices have three dimensional configurations, which increase the packing density of the LSI. However, the process for fabricating such devices include an epitaxial and a V-groove process which require a larger number of fabrication steps than that of the planar-type devices.
Planar-type devices utilized for high performance LSI circuits have generally involved scaling down the physical dimensions of the transistor. The short channel lengths involved in such scaled down transistors have involved limitations from the electrical characteristics present in such scaled down devices. The limitations on such short channel device have been the following: limited drain voltage, threshold voltage (V.sub.T) falloff, and impact ionization in the drain pinchoff region. The drain voltage is limited by punch-through voltage decrease, snap back and gate field plated P-N junction avalanche breakdown. The threshold voltage falloff is limited by the drain field induced barrier lowering and the drain and source junction doping profile and substrate doping concentration. The impact ionization in the drain pinchoff region leads to hot-electron injection into the gate oxide and the substrate electron current due to secondary impact ionization.
There have been several approaches in device structures and fabrication technologies to remove some of these limitations. One fabrication technology uses a high resistivity substrate and double channel implants, where a deep implant is used to increase the punch-through voltage and a shallow implant is used to control V.sub.T. A second approach has been a diffusion self-aligned MOS transistor or a double-diffused MOS transistor. This device causes double diffusion of P-type impurities from the same diffusion window, the process yields good short channel V.sub.T falloff and a source-drain breakdown control. Yet a third approach has been a lightly doped drain-source (LDD) process and a quadruply self-aligned (QSA) process. The LDD structure introduces narrow, self-aligned N-regions between the channel and the N+ source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity. The QSA MOS device includes four mutually self-aligned areas: a narrow polysilicon gate, shallow-source/drain to eliminate short-channel effects, deep junctions for high conductance, and specific contacts to afford efficient metal innerconnection.
A need has thus arisen to develop an improved process to produce short one to two micron channel length devices without short channel V.sub.T falloff and reasonable source-drain operating voltage support.